1. Field of the Invention
The present invention generally relates to a liquid crystal electro-optical (display) device, and particularly, to an active matrix liquid crystal electro-optical (display) device (referred to simply hereinafter as "LCD") using a thin film transistor (referred to simply hereinafter as "TFT") and to a process for fabricating the same.
2. Description of the Related Art
Active matrix LCDs are widely used in color LCDs having a large number of pixels, because they not only can suppress cross talk among the pixels, but also enable high speed driving.
In active matrix LCDs, the pixels are each driven individually by the corresponding TFTs. The TFTs, in turn, are driven by a plurality of wiring patterns formed in rows and columns on a glass substrate constituting the display panel of the LCD. Generally, the wiring patterns are formed by depositing a low-resistance aluminum (Al) layer on the substrate, and then patterning the Al layer by means of wet etching. A higher aperture ratio can be achieved by decreasing the wiring pattern width. Recent studies have focused on performing patterning by a better and more controlled dry etching process.
Attempts to carry out dry etching using a high frequency electric field on an insulator, i.e., the glass substrate, however, sometimes generate charge up on the substrate resulting in induced discharge among the wiring patterns. Such a discharge could damage the fine wiring patterns. Alternate approaches that prevent charge up from occurring are sought.
FIG. 6 shows a wiring pattern formed on a glass substrate 10 in a conventional active matrix LCD.
FIG. 6 shows a gate driver 11 formed on a glass substrate 10. A plurality of gate bus patterns 11.sub.1, 11.sub.2, 11.sub.3, . . . 11.sub.n, made of Al or an Al alloy, extend from the gate driver 11 along the row direction. A data driver 12 is formed on the glass substrate 10, and a plurality of data bus patterns 12.sub.1, 12.sub.2, 12.sub.3, . . . 12.sub.n, also made of Al or an Al alloy, extend from the data driver 12 along the column direction. Gate bus patterns 11.sub.1, 11.sub.2, 11.sub.3, . . . 11.sub.n constitute the patterns of a first layer, while the data bus patterns 12.sub.1, 12.sub.2, 12.sub.3 . . . 12.sub.n constitute the patterns of a second layer. TFTs are formed so as to correspond to respective crossing points of gate bus patterns 11.sub.1, 11.sub.2, 11.sub.3, . . . 11.sub.n with data bus patterns 12.sub.1, 12.sub.2, 12.sub.3 . . . 12.sub.n. The crossing points define a TFT matrix. Furthermore, a connection pad 13 is formed in the substrate 10 in order to electrically connect the substrate 10 with another substrate (not shown in the figure) disposed opposed thereto.
Discharge attributable to the charge up occurs in the hatched region shown in FIG. 6 when dry etching gate bus patterns 11.sub.1, 11.sub.2, 11.sub.3, . . . 11.sub.n or data bus patterns 12.sub.1, 12.sub.2, 12.sub.3 . . . 12.sub.n. This charge up could, due to plasma discharge, damage the gate bus patterns 11.sub.1, 11.sub.2, 11.sub.3, . . . 11.sub.n or the data bus patterns 12.sub.1, 12.sub.2, 12.sub.3 . . . 12.sub.n. Dielectric breakdown of the gate insulating film is generated which can cause element failure when a high electric field is locally applied to the gate bus patterns 11.sub.1, 11.sub.2, 11.sub.3, . . . 11.sub.n. Dry etching is widely employed in the fabrication of Si LSIs as well as for so-called SOI structures. However, in the case of LCDs, the size of the substrate 10 is too large and dry etching generally proceeds from the periphery. Accordingly, the peripheral region represented by hatched lines in FIG. 6 is exposed to plasma for a particularly long duration of time.
As a solution, it has been proposed circumventing the discharge. This may be done by forming, during LCD fabrication, a short ring 14, by using a short circuit in the gate bus patterns 11.sub.1, 11.sub.2, 11.sub.3, . . . 11.sub.n and in the data bus patterns 12.sub.1, 12.sub.2, 12.sub.3 . . . 12.sub.n. The short ring 14 is removed upon the completion of the LCDs, i.e., at the point during the fabrication each of the panels are cut apart. Each of the data bus patterns 12.sub.1, 12.sub.2, 12.sub.3 . . . 12.sub.n are connected to the short ring 14 at contact holes 14a.
However, in order to achieve yet higher performance, definition and resolution, it is important to further reduce the resistance of the wiring layers and to further narrow wire width. The short ring 14 of FIG. 6 has been insufficient for lowering discharge.
It has been found that damage attributed to a discharge occurs frequently when a metal having a low resistivity, such as Al, is employed in the wiring layer, as well as in fine wires having a width as narrow as about 3 .mu.m. This may be explained as follows. When a metal having low resistivity is exposed to a plasma, the metal is more apt to suffer local concentration of electric field because the electric field applied to the metal is hard to attenuate. Moreover, an electric field tends to concentrate at the portion having a finer dimension.
The problem of damaged wiring patterns from plasma discharge is particularly serious when fabricating a high resolution LCD using a large area substrate, a low resistivity metal such as Al as the wiring material, and when employing dry etching to form the wiring pattern. Furthermore, plasma discharge not always occurs only when performing dry etching. For instance, the source and drain of a TFT are formed by a process of ion implantation using a resist mask. Sometimes the substrate is treated in an oxygen plasma to strip off the resist which was hardened by the ion implantation. Discharge may also occur in the course of such an oxygen plasma treatment.